Penn student develops a way for computer chips to run more efficiently
President’s Sustainability Prize winner Nhlanhla Mavuso’s Fluid Silicon platform helps computer chips monitor their own performance in real time, reducing wasted energy and improving efficiency as demand for AI-scale computing grows.
2 min. read
Nhlanhla Mavuso of Fluid Silicon at work in the Moore Building.
Much of modern life runs on computer chips, but how most chips are designed leaves a lot on the table, as conventional design practices do not account for the changes that chips undergo as they heat, cool, and age. Engineers design for the worst-case scenario by forcing chips to run at elevated voltages and slower speeds, a tradeoff that wastes energy and limits performance. As demand for computing surges—especially with artificial intelligence—those inefficiencies add up.
Fourth-year student Nhlanhla Mavuso is working to make computer chips more efficient, durable, and less wasteful—finding ways to get more computing power from the hardware already in use. A student in Penn’s Vagelos Integrated Program in Energy Research (VIPER), jointly housed in the School of Arts & Sciences and the School of Engineering and Applied Science, he is developing Fluid Silicon, a platform that enables reconfigurable chips to monitor their condition in real time and operate more efficiently.
“Fluid Silicon’s adaptive approach to chip performance exemplifies Penn’s strength in applied innovation and offers a scalable path to greater efficiency and sustainability,” says Penn President J. Larry Jameson.
Mavuso, who hails from Simunye, Eswatini, has earned this year’s President’s Sustainability Prize, an award that empowers Penn undergraduates to design and undertake post-graduation projects that make a positive, lasting difference in the world. The prizes are among the largest of their kind in higher education. He will receive $100,000 for Fluid Silicon and a $50,000 living stipend.
“Nhlanhla is tackling a critical challenge in one of the world’s most energy-intensive industries,” says Penn President J. Larry Jameson. “Fluid Silicon’s adaptive approach to chip performance exemplifies Penn’s strength in applied innovation and offers a scalable path to greater efficiency and sustainability.”
How Fluid Silicon works
Mavuso explains that small variations introduced during manufacturing, temperature fluctuations, and gradual wear can change how fast a chip performs certain operations. But many chips still operate with a one-size-fits-all approach, he says, which wastes energy and performance.
Using tiny timing sensors built from resources already present on a class of reprogrammable chips known as field-programmable gate arrays (FPGAs), Fluid Silicon measures performance variations across different regions of a device with extraordinary precision, down to trillionths of a second. Software then interprets those measurements and adjusts how the chip operates, helping ensure it runs at settings matched to its actual condition rather than an idealized average.
Penn President J. Larry Jameson celebrated all the winners of this year’s Presidential Prizes at the annual PIP PEP luncheon, including Nhlanhla Mavuso of Fluid Silicon.
(Image: Eddy Marenco)
Different chips, Mavuso explains, effectively have different “fitness levels.” Like athletes training under different conditions or cars navigating different terrain, hardware does not always perform best under identical assumptions.
FPGAs provide a natural testing ground for this approach, because unlike fixed-function processors, FPGAs can be reconfigured after manufacturing, allowing new sensing capabilities to be integrated even while a workload is already running. These chips are widely used in data centers, telecommunications infrastructure, aerospace systems, satellites, and cell towers—places where efficiency gains can translate into significant energy savings.
Mavuso has already demonstrated the technology on real commercial FPGAs, where he allowed the FPGA to monitor and repair itself on the fly without interfering with user computation. Over the next year, he also plans to continue user testing, build out the team around the project, and deploy the technology at scale, in ways industry can trust.
He credits his President’s Sustainability Prize faculty mentor André DeHon—an electrical engineering professor who is a leading figure in reprogrammable chip architecture—and access to specialized computing resources through DeHon’s Implementation of Computation Group and interdisciplinary training through VIPER for shaping this work.
“I don’t think this project would be possible without Penn,” Mavuso says.
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